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Wolfspeed SPICE models are developed in LTSpice. They are validated in LTSpice by comparing behavior of the model to the datasheet curves to ensure that the model is well matched to the datasheet. Furthermore, models are tested in a variety of circuits to verify proper operation and convergence in real application circuits.

I'm trying to modify the example code provided by Wolfspeed for my project. The goal is to use the double 3-phase inverter as an asymmetrical half bridge converter, piloting each transistor of the converter independently. Then, I would like to activate/deactivate each single transistor using the toggle button from the CAN interface.

Forum_Moderator Wolfspeed Employee - Contributor Level 5. September 2024. Options.

Hi GKIM, with different thickness of the prepreg and core, the parasitic capacitance between the traces will be different. if you are going to have thickness of 0.3mm for prepreg and the core thickness of 1.1mm, that parasitic caps between layer 1 and 2, and the cap between layer 3 and 4 will increase while the cap between layer 2 and 3 will decrese.

Hey JNagat, Please see above for a slide that describes the differences between the TO-247-4L and new TO-247-4 LP packages.

Urvi_Ahluwalia Wolfspeed Employee - Contributor Level 2 November 2021 edited December 2023 in SpeedFit Design Simulator The [Devices] tab allows the user to specify system-level parameters, as shown in Figure 1, such as:

Could you please let me know how to adjust the Vth of SiC MOSFET spice models from Wolfspeed? I am trying to make simulation on paralleling connection with Vth variations. Thanks in advance. Best regards. Helong

Forum_Moderator Wolfspeed Employee - Contributor Level 5. July 2024. Options.